1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device for reducing a junction leakage current or a narrow width effect in which a threshold voltage rapidly drops as the channel width becomes narrow, using a self-aligned local field implantation technique, and a fabrication method thereof.
2. Description of the Related Art
A shallow trench isolation (STI) method is commonly used for isolation between unit cells of a semiconductor device, for example, a dynamic random access memory (DRAM) device. However, in case of the STI method, the width of an isolation region buried by a trench becomes narrower as the integration density of the semiconductor device increases, and as a result, it is not easy to fill the trench with insulating materials.
It has thus been suggested that the trench can be easily buried with insulating materials by forming a shallow trench depth. In the case where the trench is shallowly formed to improve the buried characteristics of the trench, a field transistor operates, such that the isolation characteristics between unit cells are substantially reduced. To solve this problem, after the trench is buried with an insulating material, a large dose quantity (8E12/cm2) of a p-type dopant such as boron (B) is field-ion-implanted on the entire surface of the trench and in an active region at an energy level of 100 keV. Thus, a channel stop impurity region is formed in the lower portion of the isolation region and the active region, so that the threshold voltage of the field transistor is increased and the isolation characteristics between unit cells are improved.
However, in order to increase the isolation between unit cells in the STI method, due to the large dose quantity of dopant for a channel stop implanted at a high energy level, a junction leakage current is increased due to the field profile between junction regions (source/drain regions) and a lower region of the junction region. The junction leakage current is further increased by defects in the junction region, which are caused during implantation of a dopant at a high energy level for forming the channel stop.
In order to address these problems, a number of compensation techniques have been proposed. These include a method for deepening the trench and filling the trench with a different material, a method for reducing a dose quantity during field ion implantation for implanting a dopant on the entire surface of a substrate, and a compensation ion implantation method for implanting a dopant of an opposite type in the junction region so as to compensate for the rise in dopant concentration of the junction region due to the field ion implantation.
However, it is not a straightforward operation to fill the trench by the method for increasing the depth of the trench and filling the trench with a different material, and the junction leakage current is increased by etching damage and stress which are incurred during the formation of a deeper trench. In the method involving the reduction of dose quantity during filed ion implantation, isolation between unit cells is not readily achieved due to the activation of the field transistor. Also, in the case of the compensation ion implantation method, since high-energy ion implantation must be additionally performed in a conventional ion implantation state, the leakage current is increased in the junction region due to defects caused by ion implantation damage.
In addition, a narrow width effect occurs in the STI method. In this effect, the threshold voltage rapidly decreases as with narrowing channel width, owing to the segregation of boron (B) as a p-type dopant due to defects caused at the interface of the trench during subsequent processes.
To address the above limitations, it is an object of the present invention to provide a semiconductor device having a reduction in junction leakage current and/or a narrow width effect while improving the isolation characteristics between unit cells.
It is another object of the present invention to provide a method for fabricating the semiconductor device.
Accordingly, to achieve the above object, there is provided a semiconductor device. The semiconductor device includes a semiconductor substrate in which an active region and an isolation region including a trench are formed, a spacer formed on both sidewalls of the trench, a channel stop impurity region which is self-aligned by the spacer and locally formed only at the lower portion of the isolation region, an isolation insulating layer in which the trench is buried, and a gate pattern which is formed on the isolation insulating layer and the active region.
The semiconductor substrate is preferably a p-type semiconductor substrate, and the channel stop impurity region is doped with a p-type dopant.
When the channel stop impurity region is formed only at the lower portion of the isolation region, the isolation characteristics between unit cells can be improved, and also, a field caused by a voltage applied to the junction region can be weakened, so that a junction leakage current can be reduced.
The channel stop impurity region is formed at the edges of the active region. When the channel stop impurity region is locally formed at the edges of the active region, a narrow width effect in which a threshold voltage rapidly decreases as channel width becomes narrower, can be reduced.
In order to achieve another object, there is provided a method for fabricating a semiconductor device. According to the method, a mask pattern is formed on a semiconductor substrate. Then, a trench is formed by etching the semiconductor substrate using the mask pattern as an etching mask. As a result, the active region of the semiconductor substrate is defined by the isolation region in which the trench is formed. A trench oxidation layer may be formed on both sidewalls and on the bottom of the trench by oxidizing the entire surface of the trench after forming the trench.
Next, a material layer for a spacer is formed on the entire surface of the semiconductor substrate in which the trench is formed. Subsequently, a channel stop impurity region is locally formed only at the lower portion of the isolation region by self-aligned-field-ion implanting a dopant on the entire surface of the semiconductor substrate using the mask pattern and the material layer for a spacer formed on the sidewalls of the trench, as an ion implantation mask. When the channel stop impurity region is formed only at the lower portion of the isolation region, the isolation characteristics between unit cells can be improved, and also, a field caused by a voltage applied to the junction region can be weakened, so that a junction leakage current can be reduced.
A spacer may be formed on both sidewalls of the trench by anisotropically etching the material layer for a spacer. Here, the spacer and the mask pattern can be used as an ion implantation mask for forming the channel stop impurity region.
Next, an isolation insulating layer is formed in the trench after removing the mask pattern used as an ion implantation mask. Then, a gate pattern is formed on the active region and the isolation insulating layer.
According to another embodiment of the present invention, the edges of the active region can be further exposed by further etching the mask pattern after forming the trench. In this case, the channel stop impurity region is also formed at the edges of the active region. In this way, when the channel stop impurity region is locally formed on the edges of the active region, a narrow width effect in which a threshold voltage rapidly decreases as a channel width becomes narrower, can be reduced.